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Testing Embedded Control Systems Using Hardware-in-the-Loop Simulation and Temporal Logic

Author(s):

M. Sanvido, V. Cechticky, W. Schaufelberger
Conference/Journal:

IFAC World Congress, Barcelona, Spain
Abstract:

In this paper a method for testing the implementation of embedded control systems using a hardware-in-the-loop simulator (HILS) and a temporal logic tester is proposed. The goal of the simulator is to replicate a given dynamical process, to be able to generate faults and to automatically analyze the Embedded Control System (ECS) response against a temporal logic specification. The paper explains and demonstrates this technique by using a simple example. The HIL simulation is implemented on an Oberon (Wirth and Gutknecht 1992) platform, the controller used for the example is implemented on the Java real-time platform JBed (Esmertec n.d.).

Year:

2002
Type of Publication:

(01)Article
Supervisor:



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% Autogenerated BibTeX entry
@InProceedings { SanCec:2002:IFA_161,
    author={M. Sanvido and V. Cechticky and W. Schaufelberger},
    title={{Testing Embedded Control Systems Using Hardware-in-the-Loop
	  Simulation and Temporal Logic}},
    booktitle={IFAC World Congress},
    pages={},
    year={2002},
    address={Barcelona, Spain},
    month=jul,
    url={http://control.ee.ethz.ch/index.cgi?page=publications;action=details;id=161}
}
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