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Processor-in-the-Loop (PIL) Simulation of Digital Motor Controller


Simon Soller

Master Thesis, FS13 (10288)

This master thesis resulted from the cooperation with the ETH spin-off company Plexim GmbH as industrial partner and the Control Systems Laboratory (IfA) at the ETH Zurich as academic partner. Plexim develops and distributes the software PLECS (Piecewise Linear Electrical Circuit Simulation) as a simulation platform for power electronic systems and is extending its functionality to allow so called Processor-in-the- Loop (PIL) simulations. The main task of this thesis was to extend an initial framework allowing PIL simulation for a current control of a brushless direct current (BLDC) motor with a speed control loop. There, investigations had been done of how such a cascaded control system is typically implemented on a microprocessor unit and evaluated with regards to its suitability for PIL testing. The focus was set on the two control tasks and their multi-threaded execution with different frequencies and execution times causing the fast control algorithm to interrupt the slow control algorithm. Therefore, different approaches had been developed to split these tasks to fit the step-by-step PIL simulation sequence. For demonstration and verification purpose, the cascaded control system has been implemented on a motor control development kit (DRV8312) with a F28069 ControlCARD from Texas Instruments and a BLDC motor from Anaheim Automation. The results of the three domains (Model-in-the-Loop (MIL), Processor-in-the-Loop (PIL) and real-time system) have been compared to validate the different approaches developed for PIL testing.


Type of Publication:

(12)Diploma/Master Thesis

A. Fuchs

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% Autogenerated BibTeX entry
@PhdThesis { Xxx:2013:IFA_4515
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