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Parallel MPC for Real-time FPGA-based Implementation


J.L. Jerez, G. Constantinides, E.C. Kerrigan, K.-V. Ling

IFAC World Congress, Milano, Italy, pp. 1338-1343

The succesful application of model predictive control (MPC) in fast embedded systems relies on faster and more energy efficient ways of solving complex optimization problems. A custom quadratic programming (QP) solver implementation on a field-programmable gate array (FPGA) can provide substantial acceleration by exploiting the parallelism inherent in some optimization algorithms, apart from providing novel computational opportunities arising from deep pipelining. This paper presents a new MPC algorithm based on multiplexed MPC that can take advantage of the full potential of an existing FPGA design by utilizing the provided ‘free’ parallel computational channels arising from such pipelining. The result is greater acceleration over a conventional MPC implementation and reduced silicon usage. The FPGA implementation is shown to be approximately 200x more energy efficient than a high performance general purpose processor (GPP) for large control problems.


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% Autogenerated BibTeX entry
@InProceedings { JerEtal:2011:IFA_4696,
    author={J.L. Jerez and G. Constantinides and E.C. Kerrigan and K.-V. Ling},
    title={{Parallel MPC for Real-time FPGA-based Implementation}},
    booktitle={IFAC World Congress},
    address={Milano, Italy},
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