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Timing Analyzer for the XC6200 FPGA

Author(s):

M. Sanvido
Conference/Journal:

ETH Zürich, Semester project at the Institute for Computer Systems.
Abstract:

The main goal of this work is the development of a timing analyzer for the Trianus FPGA System. The program has to be tailored for the Xilinx's XC6200 FPGA family.

Further Information
Year:

1996
Type of Publication:

(12)Diploma/Master Thesis
Supervisor:

N. Wirth

No Files for download available.
% Autogenerated BibTeX entry
@PhdThesis { Xxx:1996:IFA_822
}
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